Table 222. Apple SCC Registers (Continued)
----------------------------------------------------------------------
Offset Register Open Firmware Reg Property
----------------------------------------------------------------------
0x000 Command B
0x010 Data B
0x020 Command A
0x030 Data A
0x040 Channel B Enhancement
0x050 Channel A Enhancement
0x080 SCC Recovery Count
0x090 LTPC Start A
0x0A0 LTPC Start B
0x0B0 LTPC Detect AB
0x100 Timer A
0x110 Timer B reg[1],size=4096
0x120 Special Character 1A
0x130 Special Character 2A
0x140 Special Character 3A
0x160 Special Detect A
0x180 Special Character 1B
0x190 Special Character 2B
0x1A0 Special Character 3B
0x1C0 Special Detect B
0x1D0 Receive Mask A
0x1E0 Receive Mask B
See Section Channel A DBDMA Tx Registers reg[2],size=256
15.4.1, "Reg
ister Organi
zation," on
page 173
Channel A DBDMA Rx Registers reg[3],size=256
Channel B DBDMA Tx Registers reg[4],size=256
Channel B DBDMA Rx Registers reg[5],size=256
----------------------------------------------------------------------
Table 223. Apple SCC Legacy Registers (Continued) ---------------------------------------------------------------------- Offset Register Open Firmware Reg Property ---------------------------------------------------------------------- 0x000 Command B 0x002 Data B 0x004 Command A 0x006 Data A 0x008 Channel B Enhancement 0x00A Channel A Enhancement 0x080 SCC Recovery Count 0x090 LTPC Start A 0x0A0 LTPC Start B 0x0B0 LTPC Detect AB 0x100 Timer A 0x110 Timer B reg[1],size=4096 0x120 Special Character 1A 0x130 Special Character 2A 0x140 Special Character 3A 0x160 Special Detect A 0x180 Special Character 1B 0x190 Special Character 2B 0x1A0 Special Character 3B 0x1C0 Special Detect B 0x1D0 Receive Mask A 0x1E0 Receive Mask B See Section Channel A DBDMA Tx Registers reg[2],size=256 15.4.1, "Reg ister Organi zation," on page 173 Channel A DBDMA Rx Registers reg[3],size=256 Channel B DBDMA Tx Registers reg[4],size=256 Channel B DBDMA Rx Registers reg[5],size=256 ----------------------------------------------------------------------
Table 250. Apple SCC DBDMA Transmit Channel Status Bits (Continued)
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Bit Meaning
----------------------------------------------
s7 1= the timer has decremented to 0;
0=the timer is still decrementing
s6 1=GPIOA is low into the serial
port; 0=GPIOA is high
s5 the LTPC has detected the end of a
LocalTalk packet
s4 ... s1 not implemented
s0 Wait (externally controlled)
----------------------------------------------
Historically, all ISA interrupts were treated as +edge sensitive even though some were +level at the source (this still works). The intent of Requirement 6-3 was to propagate that model, but it didn't come out correctly.
Table 215. Controller Status Register (STA) ------------------------------------------------------------------------------------------------------------------------------------------------ Bit Normal Function Special Function ------------------------------------------------------------------------------------------------------------------------------------------------ 7 Parity Error: When set to 0, this bit indicates that the last byte of data received from the device See the Self-Test command in Ta had odd parity. When a parity error occurs, this bit is set to 1. ble 218 on page 109 for a descrip tion of these bits if an error is detected on self-test. 6 General Time-out: When set to 1, this bit indicates that a transmission was started by the device, but did not finish within the received time-out delay or was started by the controller, but the byte transmitted was not clocked out within the specified time limit. The controller indicates a time-out if: · The byte was clocked out, but a response was not received within the time limit. · The byte was clocked out, but a response indicates a parity error (bit 7 is also set) 5 Auxiliary Byte (AUXB): When this bit is a 1 and OUTB is a 1, the OUT register contains data from the auxiliary device (mouse). When it is a 0 and OUTB is a 1, it contains keyboard data or command controller response data from the 8042. 4 Keyboard Lock (KEYL): When this bit is a 0, the keyboard is locked and the password state is ac tive. When this bit is a 1, the keyboard is free. 3 Command/Data (C/D): When this bit is a 1, it indicates a command has or will be written to the IN N/A register. When this bit is a 0, it indicates that data has or will been written to the IN register C/D (Command/Data) 2 System Flag (SYSF): This bit is set to a 1 or 0 by writing to the system flag bit (bit 2) in the Con N/A troller Command byte. Refer to Table 218+1. 1 Input Byte (INPB): When this bit is a 1, the system has put data in the IN register for the keyboard N/A 0 Output Byte (OUTB): When this bit is a 1, the keyboard/mouse has put data in the OUT register. N/A If this bit is a 0, the OUT register is empty (the system has read the last byte presented in the OUT register). ------------------------------------------------------------------------------------------------------------------------------------------------
Table 216. Controller Commands (Continued) -------------------------------------------------------------------------------------------------------------------------------------------------- Code Command Description -------------------------------------------------------------------------------------------------------------------------------------------------- 0x20-0x3F Read Controller RAM Bits 5-0 of this command specify the address that the controller will use to address data returned in the output register. Internal address 0b00000 is assigned as the Controller Command Byte, re fer to Table 218+1. 0x60-0x7F Write to Controller RAM Write to Controller|Bits 5-0 of this command specify the internal address to which the controller will write. The next byte of data placed in the input register will be written to this address. Inter nal address 0b00000is assigned as the Controller Command Byte, refer to Table 218+1. 0xA4 Reserved 0xA5 Reserved 0xA6 Reserved 0xA7 Disable Auxiliary Device This command sets bit 5 of the Controller Command Byte to 1. This disables the auxiliary de (Mouse) vice interface by driving the clock line low. Data is not received while the interface is disabled. 0xA8 Enable Auxiliary Device This command sets bit 5 of the Controller Command Byte to 0, releasing the auxiliary device in (Mouse) terface. 0xA9 Check Interface to Auxiliary Checks the interface to the auxiliary device and stores the check code in the output Register: Device (Mouse) 0x00=no error 0x01=clock line stuck low 0x02=clock line stuck high 0x03=data line stuck low 0x04=data line stuck high 0xAA Self-Test The keyboard controller executes a self-test and writes 0x55 into the output Register if no error is detected. Bit 0 of the Controller Status Register is set to a 1 upon completion of the self-test. The system should allow one second for the self-test to complete before assuming an error oc curred and checking the Controller Status Register bits 7-4 for t he error indication. Bits 7-4 of Controller Status Register if error occurs: 0x1 - Valid 0xAA self-test command check 0x2 - Controller instruciton processing tests 0x3 - RAM data and addressing tests 0x4 - ROM data checksum and addressing tests 0x5 - Timer and interrupt handling tests 0x6 - Initialization routines and checks 0x8 - Self-test complete and 0x55 placed in the output register 0xAB Check Keyboard Interface Checks the interface to the keyboard device and stores the check code in the output Register: 0x00=no error 0x01=clock line stuck low 0x02=clock line stuck high 0x03=data line stuck low 0x04=data line stuck high 0xAD Disable keyboard Disables the keyboard. and sets bit 4 of the Controller Command byte to 1. 0xAE Enable Keyboard Enables the keyboard. and sets bit 4 of the Controller Command byte to a 0. 0xC0 Read Input Port Reads the input port to the keyboard/mouse and transfers the data into the output Register. Refer to Table 218+2. 0xC2 Poll Input Port (high) Reads bits 7-4 of the input port from the device and transfers them into bits 7-4 of the status reg ister. 0xC3 Poll Input Port (low) Reads bits 3-0 of the input port from the device and transfers them into bits 7-4 of the status reg ister. 0xD0 Read Output Port Reads the output port and places the data in the output register. Refer to Table 219. 0xD1 Write Output Port Writes the following data byte in to the ouput port. 0xD2 Write Keyboard Output Reg The next byte of data written to the input regiister is written to the output register, as if initiated ister by the keyboard ( clears AUXB in the status register). An interrupt occurs if keyboard inter rupts are enabled in the Controller Command Byte. 0xD3 Write Ouput Register to The next byte of data written to input register is written to the output register, as if initiated by Auxiliary Device (Mouse) the auxiliary device(AUXB in the status register is set). An interrupt occurs if auxiliary inter rupts are enabled in the Controller Command Byte. 0xD4 Write Auxiliary Device Writes the following byte into the auxiliary device. 0xE0 Read Test Input Port This command causes the keyboard/mouse controller to read its test inputs and place the results in the output register. Test 0 (T0) is connected to the keyboard clock line, and test 1 (T1) is con nected to the auxiliary device clock line. Data bit 0 represents T0, and data bit 1 represents T1. 0xF0-0xFF Send Pulses to Output Port This command pulses selected bits in the keyboard/mouse controller ouput port (to the device) for approximately 6 microseconds. Bits 3-0 of this command select the respective bits in the output port . --------------------------------------------------------------------------------------------------------------------------------------------------
Table 218+1. Controller Command Byte
-----------------------------------------------------------------------------------------------------------------
Bit Description
-----------------------------------------------------------------------------------------------------------------
7 Reserved
6 Keyboard Translate: When this bit is set to 1 the controller should translate the incoming scan from set
2 to set 1.
5 Disable Auxiliary Device: When this bit is set to 1, the |auxiliary device is disabled.
4 Disable Keyboard: When this bit is 1, the keyboard is disabled.
3 Reserved
2 System Flag: The value written to this bit is placed in the system flag bit of the Controller Status regis
ter.
1 Enable Auxiliary Interrupt: When this bit is set to 1, the controller generates an interrupt when it places
auxiliary device data in its output register.
0 Enable Keyboard Interrupt: When this bit is set to 1, the controller generates an interrupt when it places
keyboard data in its output register.
-----------------------------------------------------------------------------------------------------------------
Table 218+2. Input Port
---------------------------------------------------------------------------
Bits Description
---------------------------------------------------------------------------
7-2 User Definable
1 Auxiliary Data In: Reflects the state of the auxiliary data line
0 Keyboard Data In: Reflects the state of the keyboard driven data line
---------------------------------------------------------------------------
Table 219. Output Port
-----------------------------------------------------------------------------------
Bit Description
-----------------------------------------------------------------------------------
7 Keyboard Data Out : Reflects state of this data line to the keyboard.
6 Keyboard Clock Out : Reflects state of this clock line to the keyboard.
5 Auxiliary Device Interrupt: When this is 1 an interrupt has been generated by
the auxiliary device in the output register.
4 Keyboard Interrupt : When this is 1 an interrupt has been generated by the
keyboard device putting data in the output register or any connected device
posting a command to the output register.
3 Auxiliary Clock Out: Reflects state of this data line to the auxiliary device.
2 Auxiliary Data Out: Reflects state of this clock line to the auxiliary device.
1 Gate Address Line A20: No function in CHRP systems.
0 Reset System: No function in CHRP systems.
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