/afs/awd/work/PowerPC/reference_designs/longtrail/pass2/board.changes
BOARD CHANGES & ERRATA
This document lists the changes to the pass2 Longtrail boards. In some
cases a change may go in and then be reversed by a later change. A user
who builds at a later date may be able to eliminate labor by scanning through
the document and deriving a net change document that applies to their
build level. Labor can also be saved by correcting as many problems as
possible in the centroid data before assembly.
The second part of the document lists various errata and workarounds that
apply to the pass2 boards.
This file will be updated periodically as the debug progresses. So check
the date to see if you have a current version.
creation: 10/10/96 11/08/96
revision: 10/18/96 11/14/96
10/19/96 11/18/96
10/23/96 11/22/96
10/24/96 11/25/96
10/28/96 12/03/96
10/30/96 12/19/96
11/05/96
******************************************************************************
ERRATA/ WORKAROUNDS
-------------------
This section lists procedural changes or code work arounds which do not
require a physical change to the boards.
1) VRM JUMPERS
Some VRM cards do not operate properly when jumpers are installed
at the B-C positions on J20, page 6. There should have been no connections
between C1-2-3-4 and R992 should be omitted. The same result is
obtained by not populating the jumper whenever the specification
calls for populating a jumper at any B-C location on J20.
Most VRM cards will not have this problem and the BC locations provides
parking places for the jumpers.
2) SLOT 1 CANNOT BE BUS MASTER
The pass3 TG chip (identified by a -P4 in the legend) has a bug that
prevents the PCI arb req/gnt pair wired to slot 1 from working. Until
the chip is incremented, the slot (located nearest the processor) cannot
be used for bus master PCI cards. Place the video card here.
The Winbond chip does not support a busmaster in slot 1 either.
3) L2 CACHE INITIALIZATION PROCEEDURE CHANGED
The pass2 GG chip has a bug in transparent mode. The WT mode must be used
during the initialization. There is no functional impact. The
GG specification may be changed to eliminate tranparent mode.
Software must be careful that no reads can occur during the routine that
initiaizes the L2 by writing valid data into it because the tags power
on randomly and some line may look valid though it is not vaild.
4) IRQ 14 & 15 DO NOT WORK ON TG
TG pass3 (-P4 legend) has a bug. Do not configure audio or any ISA
device to use IRQ14 or IRQ15 until this is corrected in new silicon.
It is not critical to use IRQ15 on audio. Does not apply to WB boards.
5) ICBI and WRITE WITH KILLs CAUSE L2 TO BE CORRUPTED 11/22/96
Pass 2 GG doesnt handle ICBI correctly. The net result is that copy
back mode for the L2 will not work on 604XX type machines. 603XX
machines do not produce these transactions. In general not use
copy back L2 settings on 604xx type machines until new silicon
is avaliable. Some software may run on 604 and not produce these
transactions. Data is not corrupted in WT mode.
5) HANG ON SOME ADDRESSES 11/22/96
This does not cause a functional problem, but it does make debugging
bad code tough. MCP actually does function, but it can hang the
system in some cases. TA# is not activated on the address range that
GG reserves for another possible GG on the same 60x bus.
6) L2 WT MODE DOES NOT WORK IN PIPELINED BUS MODE 11/05/96
GG has a bug that doent allow the pipelined mode to operate in WT mode.
The work-around is not to do that.
7) SDRAM DOES NOT WORK WHEN PIPELINE ENABLED 11/21/96
GG can hang without a TA# in some cases when SDRAM is being used if
the pipeline mode is set. The workaround is not to enable pipeline
mode when using SDRAM.
8) LONG RETRY SEQUENCES MAY OCCUR 11/21/96
GG has a bug in its arbitor such that PCI devices may get retried for
up to 33 usec or more if the CPU request pattern is just right. There
is no workaround. This could cause some devices which require low
PCI access latency to overrun or underrun. The practical implication
on OSs is not known at this time.
9) INCORRECT DATA XFER ON SOME BURST READS 11/25/96
GG has a bug that can result in incorrect data being Xferred during
PCI burst reads. This is not frequent. There is no workaround.
The sceanario is that write data can be in a GG buffer. If a device
requests data from the cache line in GG buffers it may get stale data
from memory on subsequent transfers after the first.
10) L2 CACHE TIMING INCORRECT 11/25/96
GG has a bug wherein the OE# of the cache is brought out at the same clock
as TA#. This does not allow enough time for data setup at the CPU.
It may be possible to skew timings enough to work temporarily, but the
design must be changed. The workaround is to select cache modules with
OE# time of <,= 5ns. Several particular cache types work well enough
for prototype work.
11) PCI INFINITE RETRYS 11/25/96
GG has a bug that can lead to a hang with infinite retrys when the
L2 is enabled (CB mode) and a bus master is active. There is no work
around except not to enable the L2 in CB MODE.
The situation has been seen in WT mode, but it is very infrquent and
may or may not be the same bug.
12) 0000XXXX DATA CORRUPTION 12/19/96
WB pass A4 has a bug wherein it can put out PCI cycles with errenous
address 0000xxxx. This occurs when DMA overrun is about to occur because
of some latency on the PCI bus.
Currently we believe this bug will only occur when provoked by a GG bug
that can cause the TRDY# from an ISA DMA cycle to memory to be delayed.
This delay can occur when a number of operations are queued in GG.
The work-around is to run all DMA in compatible mode timing. This reduces
the probablility of an overrun by slowing the ISA cycles.
13) PROCESSOR HANG BUG 12/19/96
Some 604ex Power PC processors have a bug that can cause them to hang
if a cycle has the AACK# delayed until at or after the last TA#.
GG does exactly this on MACROM cycles.
The work around is to move the jumpers at J23 positions 4 & 5 to the
B-C side. This selects normal mode and the hang does not occur.
There is 1-2% performance dedgedation until the AACK timing is changed
in a new silicon revision and NODTRY# mode can be used again.
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CENTROID PROBLEMS AT PASS 2 FIRST BUILD (AUSTIN BOARDS)
------------------------------------------------------
1) The following parts were intended not to be populated. They show up in
the Cadence design files as ordinary parts. They are not needed when
the CS4263 is used. They are only populated if a CS4232 is used:
(Population has no effect on operation; the other componets on that
page are not populated and are so marked in the design files)
U11, U46
ASSEMBLY PROBLEMS AT PASS2 FIRST BUILD (AUSTIN BUILD)
-----------------------------------------------------
1) The national '308ibn version was not ordered in time. A '308ibm version
was substituted. Use '308ibn (Phoenix code) if possible.
Software impacts are expected to be zero to minimal.
2) The bom called for 6v & 10v decoupling caps for the large electrolytics
25v caps where substituted.
3) The wavetable connector (J26) did not arrive in time. Some boards were
built without this connector.
4) The Hydra-3 parts were not available. Hydra-2 parts were substituted.
Hydra-3 is required for MACOS to function 100%.
OTHER PROBLEMS WITH THE PASS2 CADENCE DESIGN FILES
--------------------------------------------------
1) The board footprint for U6 is too big. Careful hand assembley is required.
The physical library was corrected, but we failed to refresh the board
file.
2) The silk screen has an error at ????
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BOARD CHANGES (called ECs in IBM language)
---------------------------------------------
This section lists actual physical changes to the boards.
EC#1 - 10/2/96 CHRP FLOPPY CONNECTIONS
-----------------------------------------
REASON:
Make the connections on the mother board consistant with the chrp spec for
floppy cable. Pin 6 is supposed to be dsk_present# and is supposed to
connect to pin 99 of the '308 which is the dsk_chng# pin)
- This ec was implemented in the centroid data for the Austin builds.
The ec is shown in the schematic with text. It is not in the Cadence design
files.
CHANGE: SIGNAL
------
REMOVE R1006 PAGE 26 DRATE0
ADD 0-OHM R1005 PAGE 26 DSK_CHG*
REMOVE R1002 PAGE 30 DRATE0
ADD 0-0HM R1000 PAGE 30 DSK_IN_PLACE*
EC#2 10-4-96 MISSING TWO PULLUPS
----------------------------------
REASON :
A)
A documentation error in the PGA pin descriptions caused the schematic
symbol to have an error. Pin C09 (page4) should be labeled chstp_in*
and pin E09 should be ckstp_out*. No pullup resistor is then on ckstp_in*
Therefore a pullup must be added at M4-C09.
The connections to pin E09 are ok. Do not change them. Page 5
B)
We forgot to include a pullup on the AACK# signal. The debug probe pulls
the signal down and confuses either gg or the cpu. Page 4.
CHANGE:
Add a 1.5k pullup resistor at m4-c09 (back side) to 3.3v at m4-d10
page 5
Add a 1.5k pullup resistor at m4-k03 (back side) to 3.3v at m4-k04
page 4
For protection, be sure resistors do not extend above the pins .
*******************************************************************************
EC# 3 10/11/96 TEMP PULL DOWN ON IRQ 14,15
DO NOT INSTALL EC #3
REASON: TG has a bug in the IRQ logic. If IRQ14,15 are not pulled down
then the output IRQs at pins 18,19 will be continuously asserted.
CHANGE:
Lift and isolate RP43 pins 3,4 page 25
Connect lifted pins at RP43 pins 3,4 to ground at nearest gnd pin or via.
NOTE: This EC will be removed when corrected silicon is obtained. It
applies to pass 3 (-P4 notation on part) TG.
ec#3 is on hold - pending more TG info
******************************************************************************
EC #4 POTENTIAL COLLISIONS ON SD BUS DURING DMA
REASON:
TG does not do 32 bit decodes on its ROMCS#. Therefore when DMA operations
are in progress, ROMCS# could activate and cause either a collision on the
SD bus or a write into NVRAM. This is because ISAMEMR# and ISAMEMWR#
also activate during DMA cycles. -- SMRMR# & SMEMW# also
Therefore the ROMCS# pin 119 from TG must be inhibited with the AEN signal
during DMA cycles. Change affects page 22 and spares on page 41.
This EC may or may not apply to Winbond parts, but it is safest to always
do the EC.
CHANGE:
1) Lift and isolate U25 pin 11- CSROM p22
2) Lift and isolate U25 pin 1 spare p41
3) Lift and isolate U30 pin 4 spare p41
4) Lift and isolate U30 pin 5 spare p41
5) Wire U25 PAD-11 to U30 lifted pin -5 CSROM p22 (U25 pad not pin)
6) Wire U25 pin2 to U30 lifted pin -4 AEN# p22
7) Wire U34 pin2 to U25 lifted pin -1 AEN p22
8) Wire U30 pin6 to U25 lifted pin -11 GatedCS p22
******************************************************************************
EC#5 ASSEMBLY PROBLEM
This is not a change to the design. The first batch of boards
from Austin assembly had a consistent assembly error.
This keeps IDE from working.
CHECK AND ADD IF MISSING:
R113 - 82 ohms 603 package
R117 - 82 ohms 603 package
R565 - 82 ohms 603 package
R569 - 82 ohms 603 package
(these are near the IDE connectors)
*******************************************************************************
EC#6 MA PINS AT THE MEMORY DIMMS SWAPPED; CAUSES SDRAM TO FAIL
SDRAM did not work because the MA pins going from GG to the DIMMs
were pin swapped. We were not aware of the special encodings of
these pins. They may be swapped on EDO, but not for SDRAM. We allowed
pin swapping and should not have done so.
See pages 10, 14 of schematics. Note that with these changes, the net
names of these MA lines are not correct, but the signals connect
correctly. This can be corrected in the schematics without changing
connectivity.
CHANGE:
Lift and isolate pins U12 - 149, 159, 162, 163, 164, 165 & 166
Connect as follows Name Name should be:
U12 lifted pin 149 to U12 pad 163 MA4 MA0
U12 lifted pin 166 to U12 pad 164 3 1
U12 lifted pin 165 to U12 pad 166 1 2
U12 lifted pin 164 to U12 pad 165 2 3
U12 lifted pin 163 to U12 pad 159 6 4
U12 lifted pin 162 to U12 pad 149 0 5
U12 lifted pin 159 to U12 pad 162 MA5 MA6
********************************************************************************
EC#7 SELF-POWERED EXTERNAL SCSI DEVICES INTERFERE WITH LT TURN-ON LOGIC
10/17/96 ( SEE ALSO EC #15 )
This a minor problem and only affects machines having externally
powered SCSI devices attached.
The fused 5v net was incorrectly connected such that power from the
external term power line in the SCSI cable can reach the terminators
and and some other components when LT power is off. The FUSED_5V net
should be separate from the EXT_TERM_PWR net. On page 19 diode-
connect FUSED_5V to CR4 pin 2 rather than CR4 pin1. The following
instructions accomplish this result.
CHANGE
Lift and isolate L40 pin 1
Lift and isolate L41 pin 1
Lift and isolate CR4 pin 1
Add wire from L40 lifted pin 1 to L41 lifted pin 1
Add wire from L40 lifted pin 1 to CR4 lifted pin 1
(wire now connects L40-pin1, L41-pin1 and CR4-pin1)
Find a diode of type SFPV54VL or equivalent (most any diode)
Wire this diode like this:
CR4- pin&pad 2 ------ >| ------- CR4 pad 1
*******************************************************************************
EC#8 MISSING PULLUPS ON TWO SIGNALS 10/18/96
Missed pullup resistors at MCP#, GBL# signals page 4,5
Missed pullup resistors at BR1# signals page 10
It is likely that no consequence of this will be seen, but it is
not good practice to leave these pins floating.
CHANGE:
Add a 10k pullup resistor between M4.D15 and 3.3v at M4.D14 MCP#
Add a 10k pullup resistor between M4.F05 and 3.3v at M4.F02 GBL#
Add a 10k pullup resistor between U12.123 and 3.3v at U12.120 BR1#
*******************************************************************************
EC#9 PAL FIX for GG MEMACK PROBLEM 10/23/96
The 2nd pass GG chip has one or more situations when it asserts
MEMACK# prematurely in response to FLUSHREQ#. Lockup or various
kinds of data corrucption when ISA DMA is running. The PAL operates
to interrupt the MEMACK# coming from GG and only pass along a
MEMACK to TG whenever the PCI is quiet after 48 clocks. This gives
GG an opportunity to flush its buffer. The PAL may not handle 100%
of the situations and this EC may be refined shortly
CHANGE:
Solder down a 28 PLCC Pal socket at site S4.
Lift and isolate U12.184 (MEMACK# from GG to PAL)
Wire U12.184 PAD to S4.20 (MEMACK from PAL to TG)
Wire lifted pin U12.184 to S4.6 (MEMACK# from GG to PAL)
Wire U12.185 to S4.2 (PCI_CLK to PAL)
Wire U12.182 to S4.3 (CPU_REQ# to PAL)
Wire U12.183 to S4.4 (FLUSHREQ# to PAL)
Wire U12.217 to S4.7 (FRAME# to PAL)
Wire U12.179 to S4.9 (CPU_GNT# to PAL)
Wire U12.177 to S4.28 (+5VCC to PAL VCC)
Insert PAL - Name=GRDOG
*******************************************************************************
EC# 10 UNDERSHOOT ON ISA CONTROL SIGNALS 10/23/96
---- DO NOT INSTALL THIS EC ----
TG does not have edge rate controlled drivers on the ISA signals.
Approximately 2 v of undershoot was observed on ior and iow. No
error has been definately attributed to this problem, but the
edges should be slowed in order to reduce undershoot.
We will use series damping resistors with a high value to achieve
this result. page 21
CHANGE:
Lift the following pins and place a 100ohm resistor from pin to pad at:
---- DO NOT INSTALL THIS EC ----
1) U18.138 smemr#
2) U18.137 smemw#
3) U18.139 iow#
4) U18.140 ior#
5) U18.141 memr#
6) U18.142 memw#
7) U18.135 iochrdy#
8) U18.168 bale#
*******************************************************************************
EC # 11 CHANGE TO WINBOND CHIP 10/24/96
The TG version 3 chip has a problem with the arbitor that causes
hangs while running the diagnostic program whenever DMA is enabled. In
order to continue validation of the board and the GG chip, it is necessary
to change at least a limited number of boards to the WB part.
The A3 step WB 553 chips do not support decoding the PowerPC reset vector
address on the PCI bus. The A4 step chips available mid November will not
have that problem. Until the A4 step chips are available, a change must
be applied to the board to allow the use of an interposer card called
the MRA2 card in the MACROM socket. The MRA2 card holds a boot ROM
which is accessed on the CPU bus. This EC only changes the part. EC#12
is necessary if the part is not A4.
CHANGE
Remove U18 if U18 is a TG part or if U18 is an A3 step '553 and A4
step parts are available
Add Winbond '553 chip at U18
Step level A4 if available -- identifying markings = ?
Step level A3 otherwise -- identifying markings = 615TB25489060
(6XX where XX >15 and < ?? identifies
A3 step)
*******************************************************************************
EC #12 ENABLE THE MRA2 CARD WITH ROM ON CPU BUS 10/24/96
This EC is explained above. It is only necessary to do this EC
if the A3 step part is used. There is a reasonable probability
that SDRAM may not run at 66 MHz with this EC.
The EC wires 3 address lines and a CS# for the boot ROM to the
MRA2 card. It also changes the straps at GG so that it boots from
the CPU bus and expects an 8bit ROM.
CHANGE
Check U18 - If it is a step 4 Winbond '553 chip omit this change entirely.
Step A4 is identified by ///////
IF the A3 step is being added then: Add 100pf cap
from U18.22 (PCIRESET#) to GND at U18.24.
NAME ACTUAL FUNCTION
Add wire J13.28 to J8.36 MA5 MA6/RA0 **
Add wire J13.29 to J8.120 MA7 MA7/RA1
Add wire J13.110 to J8.37 MA8 MA8/RA2
Add wire J13.50 to U12.175 n/c ROMCS1#
Lift and isolate RP32.5 strap gg for CPU ROM
Wire lifted pin of RP32.5 to RP32.7 3.3v
Add 10k pulldown R from U5.116 to nearby GND (C453.2) GD3,2=0,1= 8bit
Add 10k pullup R from U5.117 to nearby 3.3v (C416.1) GD3,2=0,1= 8bit
Install the Boot ROM in the MRA2 card.
Place the jumper on the MRA2 card between the pins closest
to the Boot ROM socket.
** The signal names may be confusing to the logic engineer. Due to
pin swaps & EC6 the signal names at MA0-8 are mixed up. The net result of
EC#6 and this EC is to wire the following connections:
{U12.159 to damping resistor to DIMM.35 to J13.28 rom addr 0
U12.158 to damping resistor to DIMM.120 to J13.29 1
U12.157 to damping resistor to DIMM.36 to J13.110} 2
********************************************************************************
EC#13 SCHEMATIC ERROR AT PC87308 GPIO BITS 13, 14
There is a wiring error on the schemtics page 27 that got by undetected.
It was not intended for the schematic connections to be as shown at
pins U15.152 and U15.153. There should be no connection between these
pins and the VAUX net. If GPIO 13 or 14 were driven low by software,
damage to U15 could occur. Boo.
CHANGE:
Lift and isolate U15.152
Lift and isolate U15.153
Lift and isolate U30.12
Lift and isolate U36.4
Wire from lifted pin U15.152 to lifted pin U30.12
Wire from lifted pin U15.153 to lifted pin U36.4
*******************************************************************************
EC14 BACK PATH AT U34.9
There is a possible path from VAUX when +5VCC is low through pin 9
of U34. There should be a resistor in series with this pin to limit
back current into U34.
CHANGE:
Lift and isolate U34.9
Wire a 10k resistor between U34.9 PAD and U34.9 pin
********************************************************************************
EC#15 -- COMPLETE EC #7-CONNECT THE SCSI TERMINATOR TO THE TERMPWR LINE 11/08/96
The SCSI terminator should be fed from the TERMPWR net.
This EC connects the SCSI terminator common power pin to the
net that feeds the external term power net. Additional caps to ground
are added to the termpower net and a discharge resistor is added.
The terminator will be powered if an external device is on and the
system is off.
CHANGE:
Lift and isolate U16.20
Wire lifted pin U16.20 to lifted pin L41.1 (L41.1 was lifted in EC #7)
Add a 10k resistor from lifted pin L41.1 to GND (L40.1 and L41.1 were
connected in EC#7 -
leave this connection
there)
Add a 220 uf cap from lifted pin U16.20 to GND.
Add a 0.1uf cap from lifted pin U16.20 to GND
********************************************************************************
EC#16 -- CHANGE WINBOND A3 STEP TO WINBOND A4 STEP
With these parts it is not necessary to have the MR2A interposer card.
The boot address range is decoded to ISA. The A4 step also corrects some
problems when concurrent DMA devices are running. IF EC #12 has been
installed, it must be removed.
CHANGE
Inspect the date code on the Winbond chip. If it is earlier than
644 then replace it with an A4 part, date code 644 or greater.
REVERSE EC# 12 if it has been installed
Delete 100pf cap from U18.22 (PCIRESET#) to GND at U18.24.
Delete ec wire J13.28 to J8.36
Delete ec wire J13.29 to J8.120
Delete ec wire J13.110 to J8.37
Delete ec wire J13.50 to U12.175
Delete ec wire from lifted pin of RP32.5 to RP32.7
Remove isolation at RP32.5 and resolder pin to pad
Remove 10k pulldown R from U5.116 to nearby GND (C453.2)
Remove 10k pullup R from U5.117 to nearby 3.3v (C416.1)
Remove the MRA2 card from the MACROM socket and place the ROM in
the socket on the motherboard
*******************************************************************************
EC#17 IMPLEMENTATION ERROR AT RISCWATCH INTERFACE
The connection at pin 1 of U29 on page 5 is wrong. The signal HRESET_CPU#
should have been connected there instead. The 603 RISCWATCH will not
work this way.
CHANGE:
Lift and isolate U29.1
Wire from isolated pin U29.1 to U29.8 (HRESET_CPU#)
*******************************************************************************
EC#18 PULLUP AT SHD# SIGNAL TOO WEAK 11/18/96
*** THIS CHANGE MAY BE OMITTED, DETERMINED NOT NECESSARY ***
The RC time constant for restoring SHD# after it activates on a snoop
may be too long. No actual problem has been attributed to this, but
it is safer to use a smaller pullup for this signal. There is potential
for metastibility.
CHANGE:
Replace R977 (now 10k) with a -- 1.0K -- resistor (auto numbered net name)
(SHD#)
********** DETERMINED THAT SHD# DOES NOT ACTIVATE ***********
*******************************************************************************
EC # 19 AUDIO CHANGE
The EEPROM in the audio section has erroneous code. In order to bypass
this problem temporarily until a long-term EC strategy is decided, the
EEPROM is disabled by lifting the power pin. Note that it is not
necessary to apply this EC but does not hurt to apply it to the original
Austin-built boards. The UMAX-built boards require the EC.
CHANGE:
Lift and isolate U58 pin 8.
EC #20 BWE# CONNECTED WRONG AT L2 SOCKET 12/20/96
Some later Coast-compatible cache cards place a pulldown resistor on the
BWE#. We have this connected to the same pullup resistor as the CWEs.
These cache cards do not work. The change is to weakly pull up BEW#
with a separate resistor. Page 8.
Note some cache cards have been modified so that they will work
without this EC.
CHANGE:
Cut the trace or isolate the pin at J12.18
Add a 100k resistor between isolated pin J12.18 and 3.3v
EC#21 EXTRA DECOUPLING CAPS AT PROCESSOR
This EC is added in order to test the theory that the decoupling may
have something to do with low reliability of nsome board. It has not
been proven that there is or is not a problem.
CHANGE
Add .1uf caps directly between pins. Use X7R type caps.
2.5v gnd
M4.A11 M4.B10 avdd
M4.M11 M4.L11
M4.M07 M4.L07
M4.L12 M4.M12
M4.L10 M4.M10
M4.L08 M4.M08
M4.L06 M4.M06
M4.K11 M4.K12 >
M4.K09 M4.L09
M4.K07 M4.L07
M4.J10 M4.K10
M4.J08 M4.K08
M4.H11 M4.J11
M4.H09 M4.J09
M4.H07 M4.J07
M4.G12 M4.H12
M4.G10 M4.H10
M4.G08 M4.H08
M4.G06 M4.H06
M4.F11 M4.G11
M4.F07 M4.G07
*******************************************************************************
END OF BOARD CHANGES
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