*** Preliminary ***
LONGTRAIL-2 PLACEMENT/WIRING GUIDE (version 2)
==================================
****************************************************************************
CHANGE HISTORY
13Aug96
-------
VLSI not says that GGD clock should have same timeing as GGA clk
(no lead required any more). The section on clock lengths is modified.
06Aug96 Ver 2
-------------
(#) at the beginning of line indicates changes in version 2 (from ver 1)
01Aug96 Ver 1
-------------
Original release
****************************************************************************
I. RAW CARD
========
General guide:
- 2S2P (2 signal planes & 1 voltage plane & 1 ground plane)
- Layup/cross-section
===================== S1 (signal plane 1/top)
===================== Ground plane
===================== Voltage plane (+2.5v,+3.3v,&5v)
===================== S2 (signal plane 2/bottom)
- Controlled impedance: Zo = 50-70 ohms
- Minimum line width=6 mils (0.006" ," means inches);min line space=6 mils
- Card thickness = 0.062" +/- 0.005"
II. PLACEMENT
=========
General guide:
- Use our raw card drawing (dated 24Jul96) for ATX-board form factor,
component height restrictions, and locations of
tooling holes, PCI+ISA connectors, audio conn., SCC conn, SCSI conn,
serial1-2 conn, and ADB/MouseKeyboard conn.
- Damping/series resistor should be placed near its source (driver)
Our shematics reflects this practice
- Pullup/pulldown resistor usually is placed near its source, but
placement is not critical as long as its placement doesn't lengthen
total net length.
- High frequency caps (ie. 0.01/0.1uF): their voltage pins should be placed
close to module supply voltage pins. Minimize
- Aluminium caps (ie.82/150uF): spread evenly within its voltage plane
- 4-elment RPACK: can reassign pin for wirability as long as input-output
still pair together; if discrete resistors are better for wirability,
freely break rpack into discretes; True for combine discretes
to RPACK. If you reassign pins, you must provide us backannotation
information for schematics.
- Inductor-Capacitor (ie. L44,C68-71)
connecting between different ground types:
bridge these elements across the boundary of specified ground islands.
- Place crystal/oscillator close to X1/X2/CLK pins
III.ROUTE/WIRE
==========
1) POWER (Voltage/ground) PLANE
a/ Voltage plane: on this plane, there should be:
*************
- An +2.x voltage island for CPU core (our schematics p.6, netname
VRM_VDD) and VCCP pins of VRM40 connector J11. This island
should have 0.5" line width & cover M4 OVDD pins and J11 VCCP pins.
Place J11 close to M4. High-freq caps should be carefully
placed at M4 & J11 & bridge connecting J11-M4. See illustration
in schematics p.6 & sketch below.
Placement note: place VRM J11 close to CPU M4 & turn J11 in such
a way that when VRM module plugged in, tall components on VRM
module face away from CPU M4.
- An +3.3V voltage island for CPU VDD pins (our schematics p.6, netname
VDD3_3V or +3.3VDD logic symbol), GG2A , GG2D, L2, MACROM J13, and
PCI slot1-4 connectors.
- An +5.0V "big" voltage island for all +5v devices.
Note: GG2A U12, L2 J12, & MACROM J13 which reside in +3.3v island
have few 5v pins. Connect these +5v pins with fat traces
(10-12 mils) on surface (top/bottom) signal planes
- An 100-mil trace for +12v; preferred to have this 100-mil +12v
trace on surface (top/bottom) layer. Try to connect +12v pins
with this 100-mil "island" with fat traces instead of dividing
+5v island into small pieces.
- An island for audio GROUND (net name "gnda") which covers all
analog grounds.
*** Notice **** this audio ground island is still part of volt plane
- An island for chassis GROUND (net name "chassis") which covers all
chassis/earth/ocean grounds at back I/O connectors. There is
one mounting hole MH7 (schematics p.41) connects to chassis
ground via resistor R37. Place MH7 at coordinate (x,y)=(1.2",11.65")
which is near J14 connector (refer to raw card for MH7 location).
***Notice **** this chassis ground island is still part of volt plane
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+ | +
+ Audio GROUND | Chassis/Earth GROUND +
+--------------------------------------------------------------- +
+ +12v (100mil) +
+ ---------------------------------------------------ATX PWR CONN+
+ +5v +5v | | +
+ |3.3v|+5v +
+ ---------------------------| | +
+ | +3.3v island | +
+ ----------------| | +
Voltage + | --------- | +
Plane + | J11--+ +-- | +
+ | PCI slot1-4 DIMMs |2.x| | +
(not to + | | | | +
scale) + ----------------| GGD -+ +- | +
+ | |+2.xV|M4 | +
+ | | | | +
+ | GGA ------- | +
+ | CPU | +
+ ________________________________| +
+ +5v +
+ +5v +5v +
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
b/ GROUND plane: on this plane, there should be:
************
- An digital ground island for all grounds execept audio and chassis
- An island for audio GROUND (net name "gnda") which covers all
analog grounds. Try to connect with other audio ground island
on voltage plane (mentioned in III.1)a/)
through as many vias as possible
- An island for chassis GROUND (net name "chassis") which covers all
chassis/earth/ocean grounds at back I/O connectors.
Try to connect with other audio ground island on voltage plane
(mentioned in III.1)a/) through as many vias as possible
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+ | +
+ Audio GROUND | Chassis/Earth GROUND +
+--------------------------------------------------------------- +
+ +
+ +
+ +
+ +
Ground + +
plane + Digital ground +
(not to + +
scale) + +
+ +
+ +
+ +
+ +
+ +
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
2) CLOCKs
Requirements (applies to a/, b/, & c/)
(i) Ground shield on on both sides unless specified otherwise
These shields need to be grounded every 2-inch interval.
(ii) Route priority=1
(iii)Route on S1 layer (over SOLID ground plane), if possible.
(iv) No high-speed signals running in adjacent channel
(v) Must have a minimum number of vias
(vi) No clock wires may be routed within 1" from the edge of board
(vii)If clock wires have to cross splits between voltage islands,
route them in the most perpendicular manner possible. Do not
run wires parallel to the split in close proximity to the split.
(ie. clkA trace OK; clkB is no good)
not OK
------------ --------------
| Volt. |clkB| |Volt |
| island1 | | |island2 |
| | | |
| clkA ------------- |
-----------| OK |-------------
(viii)Minimize number of non-clock wires cross U10 W49C65
(ix) Follow MK1420 layout application note: see MK1420 app note
p.2, dated 10/95 v.4075); will fax to you.
Note: Need to ground "optional guard ring" trace (which is
on signal plane) to digital ground. It's not clearly
shown in the app note.
a/ LOCAL BUS clocks:
Additional requirement besides aforementioned (i)-(iv) ones:
_ Match length on these nets (schem. p.15):
. W49C65CPU7 + GGD_BCLK (this net has 2 segments);
. W49C65CPU7 + GGA_BCLK;
. W49C65CPU1 + SDRAM_BCLK<2> + 3" (3" is clock length on DIMM)
. W49C65CPU2 + SDRAM_BCLK<3> + 3"
. W49C65CPU3 + SDRAM_BCLK<0> + 3"
. W49C65CPU4 + SDRAM_BCLK<1> + 3"
. W49C65CPU5 + SDRAM_BCLK<4> + 3"
. W49C65CPU6 + SDRAM_BCLK<5> + 3"
. W49C65CPU11+ SDRAM_BCLK<6> + 3"
. W49C65CPU12+ SDRAM_BCLK<7> + 3"
. W49C65CPU8 + CPU_BCLK
. W49C65CPU9 + L2_BCLK<0> + 3" (3" is clock length on L2 module)
. W49C65CPU10+ L2_BCLK<1> + 3"
b/ PCI BUS clocks:
Additional requirement besides aforementioned (i)-(iv) ones:
_ Match length on these nets (schem. p.15):
. W49C65PCI1 + SIO_PCICLK
. W49C65PCI1 + HYDRA_PCICLK
. W49C65PCI2 + GGA_PCICLK
. W49C65PCI3 + SLOT1_PCICLK + 3" (3" is clock length on PCI adp
. W49C65PCI4 + SLOT2_PCICLK + 3"
. W49C65PCI5 + SLOT3_PCICLK + 3"
. W49C65PCI6 + SLOT4_PCICLK + 3"
* U10 W49C65 layout application note: see W49C65-01
pp.11-12, dated 3/96 v.0.8); will fax to you
c/ Misc clocks:
p.15
X1_14MHZ : as short as possible
X2A_14MHZ : as short as possible
X2B_14MHZ : as short as possible
W49C65REF1 + ISA14.3181MHZ : As short as possible
W49C65REF2 + AUDIO14.3181MHZ : As short as possible
W49C65_24MHZ + SUPERIO_24MHZ : As short as possible
p.18
31.3344MHZ : As short as possible
HYDRA_31.3344MHZ : As short as possible
50MHZ : As short as possible
HYDRA_50MHZ : As short as possible
p.27
RTC_X1 : As short as possible (308 RTC clock)
RTCX2_32KHZ + RTC_X2 : As short as possible
p.32
MK33MHZ + MK_33.868MHZ : As short as possible (audio YMF289S clock)
MK_24.576MHZ + CS_24.576MHZ : As short as possible (audio 4232 clock)
MK_16.934MHZ + CS_16.934MHZ : As short as possible (audio 4232 clock)
2A) LOCAL BUS CONTROLS
Route requirements for this signal group:
(i) Route priority=2
(ii) Route on S1 layer (over SOLID ground plane), if possible.
(iii)Isolate these signals from each other and from any other
signal by a ground line or by at least 0.018" space
Signal names:
-TS + M4.1-R28.1 : As short as possible.
-DBG0 : As short as possible.
-TA + UU12.52: As short as possible.
-ARTRY : As short as possible.
-AACK : As short as possible.
-TBST : As short as possible.
2B) LOCAL BUS DATA/ADDRESS BUSES
Route requirements for this signal group:
(i) Route priority=2
(ii) Route on S1 layer (over SOLID ground plane), if possible.
(iii)DCPU<63:0> length requirement : less than 1.5"
D<63:0> length requirement : less than 7.5"
(iv) A<63:0> length requirement : less than 9"
*** Note for "sequence": net order may vary depending on final layout
Signal names:
pp.3-12
DCPU+D<63:0> : As short as possible.
Sequence: M4(604)-resistor-U5(GGD)-J12(L2)-J13(MAC_ROM)
If placement changes, route sequence needs reassignment
A<8:0,31:29> : As short as possible.
Sequence: U12(GGA) - M4(604)
A<24:9> : As short as possible.
Sequence: U12(GGA)-M4(604)-U6(buf244)-J12(L2)
A<28:26> : As short as possible.
Sequence: U12(GGA)-U24(buff244)-M4(604)-J12(L2)
-TSIZ<2:0> : As short as possible.
-TT<3:0> : As short as possible.
2C) L2
Route requirements for this signal group:
(i) Route priority=2
(ii) Route on S1 layer (over SOLID ground plane), if possible.
Signal names: (p.7-8,10)
-CA3/BAA : As short as possible
-CA4/TSC : As short as possible
-TWE : As short as possible
TAG<9:0> : As short as possible.
DTY : As short as possible
-CDOE : As short as possible
-CDWE : As short as possible
2D) GOLDEN GATE II - A & D : Memory interface
Route requirements for this signal group:
(i) Route priority=2
(ii) Route on S1 layer (over SOLID ground plane), if possible.
Signal names:(pp.10-12) all these signal needs to be as short as possible
MA13/MA11
MA12/BA1
MA11/BA0
MA<10:0> : As short as possible
-RAS4/SDCAS : As short as possible
-RAS5/SDRAS : As short as possible
-RAS/SDCS<3:0>: As short as possible
-CAS/SDDQM<7:0>: As short as possible
-GG_MWE/SDWE : As short as possible
-MWE/SDWE<2:0>: As short as possible
-GG_SDCKE1 + -SDCKE1: As short as possible
-GG_SDCKE2 + -SDCKE2: As short as possible
GGAD_GD<15..0>
GGAD_PARERR
GGAD_WBSTB
GGAD_PFULD
GGAD_PFLD
GGAD_PMRD
GGAD_PCIH
GGAD_PCIL
GGAD_DIR
GGAD_PMEN
GGAD_PMW
GGAD_SPEC
2D) GOLDEN GATE II - A : PLL circuirtry
Route requirements for this signal group:
(i) Route priority=1
(ii) Route on S1 layer (over SOLID ground plane), if possible.
(iii)Do not run high-speed signals adjecent to these signals
Signals:(p.11)
# . PVDD: this net MUST be 15mil + short & C474/C478/L56 close to U12.94/93
as illustrated below:
U12.93 ---C474.1--C478.1--L56--- +3.3v
| |
U12.94 ---C474.2--C478.2
# . AVDD: this net MUST be 15mil + short & C475/C479/L58 close to U12.98/97
U12.98 ---C475.1--C479.1--L58--- +3.3v
| |
U12.97 ---C475.2--C479.2
2E) CPU (M4) - VRM (J11)
Route requirements for this signal group:
(i) Route priority=1
(ii) Route on S1 layer (over SOLID ground plane), if possible.
(iii)Do not run high-speed signals adjecent to these signals
(iv) As short as possible
Signals:(p.6)
60X_AVDD (Place C76+C77+R58 close to M4.A11)
3A) PCI CONTROL SIGNALS
(i) Route priority=3
(ii) Route on S1 layer (over SOLID ground plane), if possible.
(iii)Sequence: U12(GGA) - U13(Hydra) - U18 (SIO)
- J1(PCI_Slot1) - J2(PCI_Slot2)
- J3(PCI_Slot3) - J4(PCI_Slot4)
*** Note for "sequence": net order may vary depending on final layout
Signal names:
-PCI_FRAME : As short as possible
-PCI_TRDY : As short as possible
-PCI_IRDY : As short as possible
-PCI_STOP : As short as possible
-PCI_DEVSEL : As short as possible
-PCI_C/BE<3:0>: As short as possible
3B) PCI DATA/ADDDRESS BUSES
Route requirements for this signal group:
(i) Route priority=3
(ii) Route on S1 layer (over SOLID ground plane), if possible.
(iii)Sequence: U12(GGA) - U13(Hydra) - U18 (SIO)
- J1(PCI_Slot1) - J2(PCI_Slot2)
- J3(PCI_Slot3) - J4(PCI_Slot4)
*** Note for "sequence": net order may vary depending on final layout
Signal names:
PCI_AD<31:0> : As short as possible
Note: PCI_AD<17-22> also becomes PCI_IDSEL for 6 PCI devices.
Thus, place R223, R99, R51, R593, R52, & R594 close to
SIO U18, Hydra U13, PCISlots J1, J2, J3, & J4, respectively &
net connecting to these resistors can be T (tea) off PCI_AD net
as long as this stub/segment is less than 1" long
4) MESH SCSI
Route requirements for this signal group:
(i) Route priority=4
(ii) Sequence: U13(Hydra) - U16 (SCSI_Term) - J16 (conn)
Signal names:
SCSI_CNTL<8:0>: As short as possible; length requirement: less than 12"
SCSI_D<8:0> : As short as possible; length requirement: less than 12"
* Placement note: place U16 (parallel term) close to Hydra U13;
Must be less than 3" away from U13.
5) FAST IDE
Route requirements for this signal group:
(i) Route priority=3
(ii) Sequence: U18(SIO) - resistor(near J40/J29) - J40(prim conn) -
J29(sec. conn)
(iv) Place damping resistors as close to J40/J29 (IDE) as possible
Signal names:
pp.22-23
IDED<15:0>+IDEPRI_D<15:0>: As short as possible; Max length: 3.0"
IDED<15:0>+IDESEC_D<15:0>: As short as possible; Max length: 3.0"
IDEA<2:0> : As short as possible; Max length: 3.0"
-IDECS0 : As short as possible; Max length: 3.0"
-IDECS1 : As short as possible; Max length: 3.0"
IDE_DRQP : As short as possible; Max length: 3.0"
IDE_DRQS : As short as possible; Max length: 3.0"
-IDEIORP : As short as possible; Max length: 3.0"
-IDEIORS : As short as possible; Max length: 3.0"
-IDEIOWP : As short as possible; Max length: 3.0"
-IDEIOWS : As short as possible; Max length: 3.0"
IDE_INTP : As short as possible; Max length: 3.0"
IDE_INTS : As short as possible; Max length: 3.0"
-IDEDACKP : As short as possible; Max length: 3.0"
-IDEDACKS : As short as possible; Max length: 3.0"
IDEIORDY : As short as possible; Max length: 3.0"
6) IBM MOUSE/KEYBOARD/SERIAL/PARALLEL
Route requirements for this signal group:
(i) Route priority=5
(ii) Short as possible
Signal names:
KYBD_DATA
KYBD_CLK
MOUSE_DATA
MOUSE_CLK
PARALLEL<16:0>
SIN1/2 (SIN1 and SIN2)
-SOUT1/2
-RTS1/2
-DTR1/2
-CTS1/2
-DSR1/2
-DCD1/2
-RI1/2
EXT_SIN1/2 (SIN1 and SIN2)
-EXT_SOUT1/2
-EXT_RTS1/2
-EXT_DTR1/2
-EXT_CTS1/2
-EXT_DSR1/2
-EXT_DCD1/2
-EXT_RI1/2
7) AUDIO
Placement note:
. Use audio jack (J18&J19) as starting point & work its way towards CS4236
by the order as shown in schematics between audio jacks &
U42 CS4236/4232 (ie. Microphone example: audio jack J19 -
inductors - choke3 - TL084 - CS4236/4232)
. RC circuitry on input side of opamp (ie. TL084/82/TDA1308)
must be placed close to pins
. Protection diodes MMBD7000LT1 (ie. CR12-24) need to be placed
nearby from audio jacks (less than 2" away)
. CS4232/4236 decoupling caps: place the following caps on TOP side
as close as possible to the corresponding U42 pin. The order of
importance is:
C381, C393, C94, C82, C193, C83, C98, C101, C95, C105, C96,C106,
then C290, C307, C327, C335, C91, C343, C354, & C370;
see schematics p.32 for placement detail
. Do not place tall audio components (ie. volt regulators U14,U22;
connectors: speaker J42, CDROM J34, jumper J38, 3D J36, int fax/mod
J35, Wave J26, game J47) along the center line of PCI/ISA slots
to prevent interference with PCI/ISA cards when plugging in;
especially PCI/ISA raw card has extension at its end
for support brackets
. Filled unused surface (top/bottom) areas with copper to better
EMC shield. Make sure to connect these copper area with analog
ground thru as many vias as possible
. 3 mounting holes in audio are non-plated holes as stated in raw
card drawing. Make sure to leave clearance around these holes
as specified.
. J26 right-angle 2x13 connector for Wave Card plugin:
- Observe x-dir distance from J26.pin1 to (0,0) per
Wave card drawing (will fax)
- Observe y-dir distance from J26.pin
to reserve sufficient room for wave card pluggin
- Observe height restriction under wave card when pluggin
Route requirements for this signal group:
(i) Route priority=5
(ii) No wires are allowed to cross into audio area unless they
are connected to a device in this area. Likewise,
audio I/O wires must remain completely inside audio area.
(iii)Priority of route within audio subsystem:
(a) Microphone (LT schem.p.35)
(b) Line-in (p.34) & CD-ROM (p.36)
(c) Line-out (p.33)
(d) Headphone (p.33)
(d) Fax/mod (p.36)
(e) Speacker(p.34)
(iv) Follow Crystal's layout recommendation pp.71-72 (will fax)
Signal names:
Short as possible
L_MIC
R_MIC
L_LINE
R_LINE
EXT_L_CD
EXT_R_CD
L_OUT
R_OUT
AUD_VREF
AUD_REFLT
8) FAT WIRES
FUSED_5V: at least 0.100" line width; requires three 16-mil vias
each time it changes to different layer so that it still can
carry 5 Amps
VCC12V (+12v): at least 0.100" line width
VC12N (-12v): at least 0.020" line width
VC5N (- 5v): at least 0.015" line width
+5V_AUX(+ 5v_aux): at least 0.020" line width
# P_9VA (+ 9v_analog): at least 0.020" line width; prefer 0.040"
# +5VA (+ 5v_analog): at least 0.020" line width; prefer 0.040"
# AUD_VREF (analog): at least 0.012" line width; prefer 0.020"
VBAT : at least 0.020" line width & as short as possible
NVRAM_VCC : at least 0.020" line width & as short as possible
9) NOISE SENSITY
Requirements
(i) Short as possible
Signals:
PWR_GD
-PWR_GD
10) TEST POINT
- Every net needs a test point.
- All test points are on back side
- Test pads should be 0.040" at least
- All test points centered on 0.075" grid or 0.050" staggered grid
* MISCELLANEOUS ITEMs
- Parallel/printer 2x20 header PINOUT:
Must change Allegro physical model to match pinout shown in shematics
p.30
Top view --------------------------
|21 40|
| 1 20|
-----------key------------
- Spare PAL/SOICs (S1-S4, schem.p.41): wire all pin out from pads;
double-via trace on bottom layer if possible
---------------------------------------------------------------------------