Low-Voltage Macintosh Toolbox ROM Card Specification
Nathan Pritchard
Howard Tanner
August 15, 1996
1. SCOPE
This document defines a 4 megabyte 3.3 Volt ROM or flash ROM on a 160-pin
DIMM for Common Hardware Reference Platform (CHRP) based systems requiring
a Macintosh Toolbox ROM. Features include:
+ Same connector as previous 5V-only design
+ Uses different power pins than 5V design
+ 3.3V-only operation for ROM and flash ROM cards
+ Chip Enable for entire device (potential for low-power standby mode)
+ Output Enable (3-state output)
+ Write Enable for flash ROM cards
+ Detect bits for DIMM presence and burst capability
+ 64-bit big endian data bus
+ Possible future expansion to 8 megabytes
This specification is based upon specifications for DIMMs by Apple
Computer, Inc. for use with MacOS.
2. CONNECTOR
Burndy PN ELF160ASC-3Z50.
This is the DIMM connector currently used in CHRP systems for 5V ROM cards.
This connector is compatible with the current Apple Macintosh ROM standard.
It provides 160 pins in 3 bays of 25/25/30 positions, through-hole solder
tails, and metal retention clips. It is designed and tested for high-speed
systems with signal rise times greater than one nanosecond.
3. CONVENTIONS
a. Endianness
The ROM address and data buses are organized in "big endian" fashion:
the lowest-numbered bit in a group has the greatest effect on the value
of the group (it is the "most significant bit") and the highest-numbered
bit has the least effect (it is the "least significant bit"). For
example, on a big endian data bus D63 is the 1's place, D62 is the 2's
place, D61 is the 4's place, etc.
b. Signal levels
A signal's active level determines whether it is "asserted" when it is
high, a logical 1; or low, a logical 0. A signal performs the function or
indicates the status given by its name when the signal is asserted. When
the active high signal "READY" is a logical 1, it is asserted and the
associated device is ready. When the active low signal "PRESENT*" is a
logical 1, it is deasserted and the associated device is not present.
Active low signals in this document are indicated by the symbol "*"
following the signal name.
4. PIN LIST
---------------------- -----------------------
Pin number | Signal Pin number | Signal
---------------------- -----------------------
80 | +5VCC 160 | +5VCC
79 | +3.3VCC 159 | +3.3VCC
78 | RESERVED 158 | RESERVED
77 | GND 157 | GND
76 | D0 (MSB) 156 | D32
75 | D1 155 | D33
74 | D2 154 | D34
73 | D3 153 | D35
72 | RESERVED 152 | RESERVED
71 | +5VCC 151 | +5VCC
70 | +3.3VCC 150 | +3.3VCC
69 | D4 149 | D36
68 | D5 148 | D37
67 | D6 147 | D38
66 | D7 146 | D39
65 | GND 145 | GND
64 | D8 144 | D40
63 | D9 143 | D41
62 | D10 142 | D42
61 | D11 141 | D43
60 | RESERVED 140 | RESERVED
59 | +5VCC 139 | +5VCC
58 | +3.3VCC 138 | +3.3VCC
57 | D12 137 | D44
56 | D13 136 | D45
---------------------- -----------------------
55 | D14 135 | D46
54 | D15 134 | D47
53 | GND 133 | GND
52 | RESERVED 132 | RESERVED
51 | RESERVED 131 | RESERVED
50 | RESERVED 130 | RESERVED
49 | RESERVED 129 | RESERVED
48 | RESERVED 128 | A9
47 | A10 (MSB) 127 | A11
46 | A12 126 | A13
45 | A14 125 | A15
44 | A16 124 | A17
43 | GND 123 | GND
42 | RESERVED 122 | BURST_CAP*
41 | +5VCC 121 | +5VCC
40 | +3.3VCC 120 | +3.3VCC
39 | RESERVED 119 | RESERVED
38 | ROMOE0* 118 | ROMOE1*
37 | FLASHWE0* 117 | FLASHWE1*
36 | RESET* 116 | MBROMEN*
35 | RESERVED 115 | ROMCE*
34 | A18 114 | A19
33 | A20 113 | A21
32 | A22 112 | A23
31 | A24 111 | A25
---------------------- -----------------------
30 | A26 110 | RESERVED
29 | RESERVED 109 | A27
28 | RESERVED 108 | A28 (LSB)
27 | GND 107 | GND
26 | D16 106 | D48
25 | D17 105 | D49
24 | D18 104 | D50
23 | D19 103 | D51
22 | RESERVED 102 | RESERVED
21 | +5VCC 101 | +5VCC
20 | +3.3VCC 100 | +3.3VCC
19 | D20 99 | D52
18 | D21 98 | D53
17 | D22 97 | D54
16 | D23 96 | D55
15 | GND 95 | GND
14 | D24 94 | D56
13 | D25 93 | D57
12 | D26 92 | D58
11 | D27 91 | D59
10 | +3.3VCC 90 | +3.3VCC
9 | +5VCC 89 | +5VCC
8 | +3.3VCC 88 | +3.3VCC
7 | D28 87 | D60
6 | D29 86 | D61
5 | D30 85 | D62
4 | D31 84 | D63 (LSB)
3 | +12VPP 83 | +12VPP
2 | GND 82 | GND
1 | +5VPP 81 | +5VPP
---------------------- -----------------------
NOTE:
D63 (pin 84) is the least significant bit (LSB) of the data bus, and D0
(pin 76) is the most significant bit (MSB). A28 (pin 108) is the LSB of
the address bus, and A10 (pin 47) is the MSB for the 4 megabyte ROM. A9
is available for future expansion to an 8 megabyte ROM module, which would
make A9 the MSB of the address bus.
5. PIN ORIENTATION
Card outline:
------------------------------------------
| |
| 25 25 30 |
| positions positions positions |
-- --- --- --
| | | | | |
------------ ------------ --------------
Front pin #: 80 56 55 31 30 1
Back pin #: 160 136 135 111 110 81
Connector (top view, with pin numbers):
|-|160 136 135 111 110 81|-|
|-|------------|------------|--------------|-|
| | | | | |
|-|------------|------------|--------------|-|
|-|80 56 55 31 30 1|-|
6. SIGNAL DESCRIPTIONS
-------------------------------------------------------------------------
| | | Active |
Pin Number(s) | Symbol | I/O | Level | Function
-------------------------------------------------------------------------
84-87,91-94,96-99, | D63-D0 | O | HIGH | Data output (or
103-106,134-137,141-144, | | | | input for flash
146-149,153-156, | | | | versions)
4-7,11-14,16-19,23-26, | | | |
54-57,61-64,66-69,73-76 | | | |
-------------------------------------------------------------------------
30,111,31,112,32,113,33, | A26-A10 | I | HIGH | Non-burst
114,34,124,44,125,45, | | | | addresses
126,46,127,47 | | | |
-------------------------------------------------------------------------
108,109 | A28,A27 | I | HIGH | Burst mode
| | | | addresses
-------------------------------------------------------------------------
128 | A9 | I | HIGH | For possible
| | | | future expansion
| | | | to 8 MB DIMMs
-------------------------------------------------------------------------
115 | ROMCE* | I | LOW | Module enable
-------------------------------------------------------------------------
38 | ROMOE0* | I | LOW | Enables D31-D0
| | | | outputs
-------------------------------------------------------------------------
118 | ROMOE1* | I | LOW | Enables D63-D32
| | | | outputs
-------------------------------------------------------------------------
116 | MBROMEN* | O | LOW | Motherboard ROM
| | | | enable
-------------------------------------------------------------------------
122 | BURST_CAP* | O | LOW | Burst capability
| | | | detect
-------------------------------------------------------------------------
37 | FLASHWE0* | I | LOW | Enables writing to
| | | | D31-D0 (for flash
| | | | versions)
-------------------------------------------------------------------------
117 | FLASHWE1* | I | LOW | Enables writing to
| | | | D63-D32 (for flash
| | | | versions)
-------------------------------------------------------------------------
36 | RESET* | I | LOW | Reset signal for
| | | | some flash ROMs
-------------------------------------------------------------------------
8,10,20,40,58,70,79,88, | +3.3VCC | PWR | N/A | +3.3V Power supply
90,100,120,138,150,159 | | | |
-------------------------------------------------------------------------
9,21,41,59,71,80,89,101, | +5VCC | PWR | N/A | +5V Power supply
121,139,151,160 | | | |
-------------------------------------------------------------------------
1,81 | +5VPP | PWR | N/A | +5V Programming
| | | | voltage (req'd on
| | | | all systems)
-------------------------------------------------------------------------
3,83 | +12VPP | PWR | N/A | +12V Programming
| | | | voltage (not
| | | | required)
-------------------------------------------------------------------------
2,15,27,43,53,65,77,82, | GND | PWR | N/A | Ground
95,107,123,133,145,157 | | | |
-------------------------------------------------------------------------
22,28,29,35,39,42,48-52, | RESERVED | N/A | N/A | Reserved for
60,72,78,102,110,119, | | | | future (and past)
129-132,140,152,158 | | | | use
-------------------------------------------------------------------------
NOTES:
- D63-D0 represent a 64-bit big endian data bus. The bus is
output-only for ROM versions but bidirectional for flash ROM versions.
- A26-A10 represent part of the big endian address bus. These bits
remain constant during burst reads. A9 is available for possible future
expansion to 8 megabyte DIMMs.
- A28 and A27 are also part of the address bus, and they are
incremented for burst reads by the ROM controller logic if the DIMM is
burst capable. Bits 32-29 are not needed in the address bus because the
DIMM can produce 64-bit output, although the system can enable each
32-bit half independently.
- ROMCE* is provided as an optional chip enable signal for the entire
module. The signal should be wired to the chip select/enable pins of the
individual ROM chips on the DIMM. The DIMM must be designed with a
pull-down resistor on the signal to be compatible with systems which do
not wire a signal to this pin.
- MBROMEN* is implemented for those systems that have Toolbox ROM on the
motherboard. The pin is tied to +3.3VCC on the DIMM, and it can be used
to disable the motherboard ROM when the DIMM is inserted. It can also
be used as a presence detect bit.
- BURST_CAP* should be low on modules which are capable of burst reads
(lower access times for reads when only the two least significant bits are
changed) and high on those which are not.
- On DIMMs using flash ROMs, FLASHWE1* and FLASHWE0* must have pull-up
resistors to be compatible with systems which do not wire signals to
these pins. It is also recommended that these signal be routed to
the card edge through a 0 ohm resistor so that they may easily be
disconnected entirely, if so desired.
- RESET* is provided for DIMMs assembled with flash ROMs that support
a reset signal. Systems that wish to support this should wire the system
reset signal to this pin. This provision ensures that the flash ROMs will
return to read-mode even if a system reset occurs during a write operation.
The DIMM must be designed with a pull-up resistor on the signal to be
compatible with systems which do not wire a signal to this pin. It is also
recommended that this signal be routed to the card edge through a 0 ohm
resistor so that it may easily be disconnected entirely, if so desired.
- The +5VCC pins are labelled for historical purposes. They must be no
connects on 3.3V DIMMs to avoid problems if they are put in 5V systems.
A 3.3V DIMM will not function in a 5V system, and a 5V DIMM will not
function in a 3.3V system.
- Systems are required to run +5V to the +5VPP pins to support flash
modules that utilize a 5V programming voltage. Systems may also run
+12V to the +12VPP pins to support flash modules that utilize a 12V
programming voltage, but it is not required.
7. ROM IMPLEMENTATION
7.1. Parts
The Hitachi Semiconductor & IC Division offers a line of low
voltage 8-Mbit CMOS mask-programmable ROMs: the HN62W448N series. Four of
these parts configured for 16-bit output will be used to produce a 4
megabyte device with 64-bit output. These ROMs are available in a 44-pin
SOP (HN62W448NFB) which is pin-compatible with the parts for the Flash ROM
implementation.
7.2. Timing
These parts offer access times adhering to current Macintosh
Toolbox ROM designs, i.e., 120 ns (minimum) standard access times and
60 ns (minimum) burst access times. Hitachi's HN62W448NFB-12 ROMs are
currently available with these access times. Parts with 100 ns standard
access times and 40 ns burst access times should be available in August
or September 1996.
7.3. I/O Loads
Parameter Symbol | Parameter Description | Min | Max | Unit |
-------------------------------------------------------------
C IN | Input Capacitance | -- | 10 | pF |
C OUT | Output Capacitance | -- | 15 | pF |
7.4. Current Draw
Sym | Description | Conditions | Max | Unit |
---------------------------------------------------------------------------
I LI | Input Leakage Current | normal operation | +/-10 | uA |
I LO | Output Leakage Current | normal operation | +/-10 | uA |
I DD | Active Supply Current | V DD = 3.6V, I DOUT = 0mA | 60 | mA |
8. FLASH ROM IMPLEMENTATION
8.1. Parts
AMD offers a line of low voltage 8-Mbit CMOS flash ROMs: the
Am29LV800 series. Four of these parts configured for 16-bit output will
be used to produce a 4 megabyte device with 64-bit output. These ROMs are
available in a 44-pin SOP (Am29LV800T-120SC) which is pin-compatible with
the parts for the ROM implementation.
Hitachi also offers a line of low voltage 8-Mbit CMOS flash ROMs:
the HN29WT800 series. These ROMs are available in the same package
(HN29WT800FP) and can be used in the same configuration.
Unless otherwise noted, the specifications that follow apply
only to the AMD flash ROM chips, but the Hitachi chips may be assumed
to have similar characteristics.
8.2. Timing
These parts for the development and debugging phase of the 3.3v
MACROM design offer standard access times adhering to current MACROM
designs, but no capacity for burst reads. AMD's Am29LV800T-120SC flash
ROMs are currently available with 120 ns standard access times. Flash ROMs
with 100 ns standard access times will eventually be available.
Hitachi's HN29WT800FP-12 flash ROMs are currently available with
120 ns standard access times. Flash ROMs with 100 ns and 80 ns standard
access times will eventually be available.
8.3. I/O Loads
Parameter Symbol | Parameter Description | Typ | Max | Unit |
---------------------------------------------------------------
C IN | Input Capacitance | 6 | 7.5 | pF |
C OUT | Output Capacitance | 8.5 | 12 | pF |
C IN2 | Control Pin Capacitance | 8 | 10 | pF |
8.4. Current Draw
Sym | Description | Conditions | Max | Unit |
---------------------------------------------------------------------
I LI | Input Load Current | normal operation | +/-1.0 | uA |
I LO | Output Leakage Current | normal operation | +/-1.0 | uA |
I CC1 | Vcc Active Read Current | CE* = 0, OE* = 1 | 35 | mA |
I CC2 | Vcc Active Write Current | CE* = 0, OE* = 1 | 35 | mA |
8.5. Programming
The new low-voltage flash ROMs offered by AMD utilize the
standard programming and status-checking algorithms designed for their
previous flash ROM products. These are described in detail in the
Am29LV800 specifications provided by AMD. The main ideas are
summarized here.
The four 8-Mbit flash ROMs can be easily erased and programmed
in parallel. Important points:
- Addresses are latched on the falling edge of ROMCE* or the corresponding
FLASHWE*, whichever occurs later.
- Data are latched on the rising edge of ROMCE* or the corresponding
FLASHWE*, whichever occurs first.
- The ROM chips are held in word-mode for 16-bit output, so only the
command values that pertain to word-mode programming are applicable.
8.5.1. Command Definitions
-------------------------------------------------------------------------------
| Bus Write Cycle |
Command |-----1----|-----2----|-----3----|-----4----|-----5----|-----6----|
Sequence |Addr |Data|Addr |Data|Addr |Data|Addr |Data|Addr |Data|Addr |Data|
-------------------------------------------------------------------------------
Reset/Read |XXXXH|F0H |RA |RD | | | | | | | | |
-------------------------------------------------------------------------------
Autoselect |5555H|AAH |2AAAH|55H |5555H|90H | | | | | | |
-------------------------------------------------------------------------------
Program |5555H|AAH |2AAAH|55H |5555H|A0H |PA |PD | | | | |
-------------------------------------------------------------------------------
Chip Erase |5555H|AAH |2AAAH|55H |5555H|80H |5555H|AAH |2AAAH|55H |5555H|10H |
-------------------------------------------------------------------------------
Sector Erase|5555H|AAH |2AAAH|55H |5555H|80H |5555H|AAH |2AAAH|55H |SA |30H |
-------------------------------------------------------------------------------
Sector Erase|XXXXH|B0H | | | | | | | | | | |
Suspend | | | | | | | | | | | | |
-------------------------------------------------------------------------------
Sector Erase|XXXXH|30H | | | | | | | | | | |
Resume | | | | | | | | | | | | |
-------------------------------------------------------------------------------
Notes:
RA = Address of the memory location to be read.
RD = Data read from location RA during a read operation.
PA = Address of the memory location to be programmed.
PD = Data to be programmed at location PA.
SA = Address of the sector to be erased. The combination of the higher
order addresses (A10-A16) will uniquely select any sector.
Reset/Read command can be used at any point during the command sequence
to return the device to read mode and reset the internal state machine.
The address values in the table must be put on the address bus at bits
A13-A28. The data values in the table must be put on the lower 8-bits
of each 16-bit ROM package being programmed. For example, for the first
cycle of a program operation to D32-D63, the value 5555H must be put on
address bits A13-A28 and the value 00AA00AAH must be put on data
bits D32-D63.
8.5.2. Operation Status
8.5.2.1. Data Polling (DQ7)
During a programming operation, attempts to read the value at the
programmed address will cause each ROM package to produce the
compliment of the data last written to its eighth bit (DQ7). Upon
completion of the operation, the data will be correct although the
other data bits make take one additional read operation to switch to
the correct values. The negation of the data at the polling bits
guarantees that the value read will not be the correct one until
after the operation has completed.
During an erase operation, read attempts at addresses being erased
will produce a '0' at the polling bits. Upon completion of the
operation, the read attempts will produce a '1' at the polling bits.
The data polling bits for the DIMM are D40 and D56 for the low word
(D32-D63), and D8 and D24 for the high word (D0-D31).
8.5.2.2. Toggling (DQ6)
During a progamming or erase operation, successive attempts to read
data from an address being progammed or erase will cause the sixth
data bit (DQ6) of each ROM package to toggle between '1' and '0'.
Upon completion of the operation, the bit will stop toggling and
valid data may be read. Either ROMCE* or the appropriate ROMOE*
toggling will cause the bits to toggle.
The toggle bits for the DIMM are D41 and D57 for the low word
(D32-D63), and D9 and D25 for the high word (D0-D31).
8.5.3. Algorithms
8.5.3.1. Embedded Programming Algorithm
For each address/data pair to be programmed:
a. Write four-cycle program command sequence, include programming
address and data.
b. Data poll device (read at the address being programmed).
c. Is the data correct? If not, return to step b.
8.5.3.2. Embedded Erase Algorithm
a. Write six-cylce erase command sequence, either chip erase or sector
erase.
b. Data poll device (read at an address being erased).
c. Is the data all ones? If not, return to step b.